Technical Field
This disclosure relates to electronic design automation (EDA). More specifically, this disclosure relates to network flow based framework for clock tree optimization.
Related Art
Clock tree synthesis refers to the process of creating a clock distribution network for distributing a clock signal to a set of sequential circuit elements in a circuit design. A circuit design may include multiple clock domains, and each clock domain can include multiple clock trees. Additionally, the circuit design may include multiple modes and corners, wherein certain clock trees or certain portions of clock trees are operational in a given mode, and wherein each corner corresponds to a particular set of operating and/or process conditions. The circuit design typically needs to satisfy timing requirements across all mode and corner combinations; therefore, the clock tree needs to be optimized across all mode and corner combinations.
The quality of the clock trees that are generated by clock tree synthesis can have a significant impact on downstream stages in the EDA flow, especially on timing closure. Hence, what are needed are systems and techniques for clock tree synthesis that can efficiently create high quality clock trees.